The subject invention is directed broadly to memory architectures, and more particularly to memory architectures in high-density or low-power applications, and will be described with particular reference thereto. It will be appreciated by one of ordinary skill in the art that the subject architecture is useful in any fetch-instruction processor application in which lower cost or higher density is advantageous.
Typical processor architectures employ a central processing unit (“CPU”) working in conjunction with both addressable and non-addressable memory. A typical, addressable memory includes two sets of lines to access specified memory locations. Address lines allow for input of a binary number that corresponds to a memory location. In an addressable memory, a particular memory location is specified by placing a binary address as a digital input on the address lines. At this point, access by the data lines is made to the specified memory location. A read-write enable (“RW”) input is typically used to signify whether data from the data lines is to be stored into the selected memory location, or read from the selected memory location. Since any address may be placed on the address lines at any given time, access is truly random in nature. Thus, an addressable memory devices is referred to as random access memory, or RAM. A non-addressable memory by comparison does not use address lines to select a particular memory location. Instead, data is written into the memory or read from the memory as a serial stream of information. An early tape drive for storage of data would be one example of a non-addressable memory device.
Low-power or compact CPUs are typically formed as microprocessor units (“MPU”). Data, which is stored in the memory, is communicated in parallel by a plurality of data lines. MPU is used herein insofar as a microprocessor unit as envisioned in the preferred embodiments. However, it will be appreciated by one of ordinary skill in the art that the subject architecture is applicable to any digital CPU/memory architecture.
During typical processor operation, a CPU provides an address in the memory device from which a particular data item or instruction is desired. The memory device retrieves the data or instruction from the selected location via the address lines, and provides that data or instruction on the data lines. Thus, the MPU is able to fetch the desired data or instruction from the device. Such an addressable memory architecture works in a random fashion, leading to its designation as random access memory RAM, as noted above.
Other conventional memory devices are not random access in nature. Such data devices may require serial access of data, such as from a tape drive, hard disk, serial data stream or the like. Given the serial nature of such data streams, it is difficult to use a sequential memory device for fetching and processing instructions or data.
Most digital processing systems are prepared to become active from an off or powered-down state. When powering up, a digital device has extremely limited capability, and must at least load a core or kernel of instructions to allow the device to engraft upon the system the functionality necessary to accomplish most conventional, computerized tasks. This is generally accomplished by having a forced memory location from which a processor will commence operation during a power-up sequence. This memory location has a set of instructions which provides the basic functionality necessary for the system. Once this initial application has been loaded and run, the system has enough intelligence to allow it to accomplish more refined tasks, such as addressing peripheral equipment, loading an operating system or commencing operation of other, selected programs.
The operation of a typical boot sequence, as noted above, requires a presence of at least a small core of RAM to allow for sequential addressing of a boot code. Random access memory is relatively expensive and requires a relatively large amount of space to fabricate when compared to serial memory devices. Such a serial memory device, e.g., NAND flash memory, is still used in hybrid RAM/NAND architecture. It would be desirable if a boot sequence could be completed from NAND memory, thus eliminating the requirement of RAM memory with its associated drawbacks.
The subject invention provides a bootable CPU that is able to use code disposed in NAND flash memory. Thus, power applications such as personal digital assistance (“PDA”), cellular phones or other compact and energy efficient electronic devices may utilize NAND flash memory with its associated benefits.
An advantage of the present invention is the provision of a processing system which utilizes less power than those employing RAM memory.
Another advantage of the present invention is the provision of a processor system that is more compact.
Yet another advantage of the present invention is the provision of compact and cooler-memory which allows for selective inclusion on the same chip substrate of that of a processing device.
These and further advantages will become apparent to others upon reading and understanding the subject disclosure.